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S34MS08G2 8 gb, 4-bit ecc, x8 i/o and 1.8 v v cc nand flash memory for embedded cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00515 rev. *g revised march 15, 2018 distinctive characteristics density ? 8 gb (4 gb ? 2) architecture (for each 4 gb device) ? input / output bus width: 8-bits ? page size: (2048 + 128) by tes; 128-byte spare area ? block size: 64 pages or (128k + 8k) bytes ? plane size ? 2048 blocks per plane or (256m + 16m) bytes ? device size ? 2 planes per device or 512 mb nand flash interface ? open nand flash interface (onfi) 1.0 compliant ? address, data and commands multiplexed supply voltage ? 1.8v device: v cc = 1.7v ~ 1.95v security ? one time programmable (otp) area ? serial number (unique id) ? hardware program/erase dis abled during power transition additional features ? supports multiplane program and erase commands ? supports copy back program ? supports multiplane copy back program ? supports read cache electronic signature ? manufacturer id: 01h operating temperature ? industrial: C40 c to 85 c ? industrial plus: C40 c to 105 c performance ? page read / program ? random access: 30 s (max) ? sequential access: 45 ns (min) ? program time / multiplane program time: 300 s (typ) ? block erase / multiplane erase ? block erase time : 3.5 ms (typ) reliability ? 100,000 program / erase cycles (typ) (with 4-bit ecc per 528 bytes) ? 10 year data retention (typ) ? blocks zero and one ar e valid and will be valid f or at least 1000 program-erase cycles with ecc ? package options ? lead free and low halogen ? 63-ball bga 9 ? 11 ? 1 mm
document number: 002-00515 rev. *g page 2 of 17 S34MS08G2 contents 1. general description ..................................................... 3 2. connection diagram .................................................... 3 3. pin description ............................................................. 4 4. block diagrams ............................................................ 5 5. addressing ............................................................... .... 6 6. read status enhanced ................................................ 7 7. read id ............................................................... ........... 7 7.1 read parameter page ......................................... .......... 9 8. electrical characteristics .......................................... 12 8.1 valid blocks ................................................ ................. 12 8.2 dc characteristics .......................................... ............. 12 8.3 pin capacitance............. ........... ........... .......... .............. 13 8.4 power consumptions and pin capacitance for allowed stacking configur ations ............................ . 13 9. physical interface ....................................................... 14 9.1 physical diagram ............................................ .............. 14 10. ordering information .................................................. 15 11. revision history .......................................................... 16 document history page ......................................... ............. 16 sales, solutions, and legal information ....................... .... 17 worldwide sales and design supp ort ............ ........ ........ 17 products ...................................................... ................... 17 psoc? solutions ............................................... ............ 17 cypress developer community . .................................. ... 17 technical support ........... .................................. ............. 17 document number: 002-00515 rev. *g page 3 of 17 S34MS08G2 1. general description the cypress S34MS08G2 8-gb nand is offered in 1.8v cc with x8 i/o interface. this document contains information for the S34MS08G2 device, which is a dual -die stack of two s34ms04g2 di e. for detailed specifications, please refer to the discrete di e datasheet: s34ms01g2_04g2 . 2. connection diagram figure 1. 63-bga contact, x8 device, single ce (top view) note 1. these pins should be connected to power supply or ground (as designated) following the onfi s pecification, however they migh t not be bonded internally. f3 f4 f5 f6 f7 f8 e3 e4 e5 e6 e7 e8 d3 d4 d5 d6 d7 d8 c3 c4 c5 c6 c7 c8 rb# we# ce# vss ale wp# nc nc nc cle re# vcc nc nc nc nc nc nc g3 g4 g5 g6 g7 g8 nc vss nc nc nc nc h3 h4 h5 h6 h7 h8 v cc nc nc nc i/o0 nc b9 a9 nc nc a2 nc nc nc nc nc vcc nc b10 a10 nc nc b1 a1 nc nc j3 j4 j5 j6 j7 j8 i/o7 i/o5 v cc nc i/o1 nc k3 k4 k5 k6 k7 k8 v ss i/o6 i/o4 i/o3 i/o2 v ss l9 nc l2 nc l10 nc l1 nc m9 nc m2 nc m10 nc m1 nc document number: 002-00515 rev. *g page 4 of 17 S34MS08G2 3. pin description notes 2. a 0.1 f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power suppl y. the pcb track widths must be sufficient to carry the currents required during program and erase operations. 3. an internal voltage detector disables all functions whenever v cc is below 1.1v to protect the device from any involuntary progr am/erase during power transitions. table 1. pin description pin name description i/o0 - i/o7 inputs/outputs . the i/o pins are used for comma nd input, address input, data input, and data output. the i/o pins float to high-z when th e device is deselected or the o utputs are disabled. cle command latch enable. this input activates the latchi ng of the i/o inputs inside the command register on the rising edge of write enable (we#). ale address latch enable. this input activates the latchi ng of the i/o inputs inside the address register on the rising edge of write enable (we#). ce# chip enable. this input controls t he selection of the device. when the devic e is not busy ce# low selects the memory. we# write enable. this input latches command, address and data. the i/o inputs ar e latched on the rising edge of we#. re# read enable. the re# input is the se rial data-out contro l, and when active d rives the data onto the i/o bus. data is valid t rea after the falling edge of re# w hich also increments the intern al column address counter by one. wp# write protect. the wp# pin, when low, provides h ardware protection against und esired data modification (program / erase). r/b# ready busy . the ready/busy output is an o pen drain pin that signals the s tate of the memory. vcc supply voltage . the v cc supplies the power for all the operations (read, program, eras e). an internal lock circuit prevents the inse rtion of commands when v cc is less than v lko . vss ground. nc not connected. document number: 002-00515 rev. *g page 5 of 17 S34MS08G2 4. block diagrams figure 2. functional block diagram 8 gb figure 3. block diagr am 1 ce (4 gb x 8) address register/ counter controller command interface logic command register data register re# i/o buffer y decoder page buffer x d e c o d e r nand flash memory array wp# ce# we# cle ale i/o0~i/o7 program erase hv generation 8192 mbit + 512 mbit (8 gb device) io0~io7 ce# we# r/b# re# vss ale vcc cle wp# io0~io7 io0~io7 ce# ce# we# we# r/b# r/b# re# re# vss vss ale ale vcc vcc cle cle wp# wp# 4 gb x8 nand flash memory#1 4 gb x8 nand flash memory#2 document number: 002-00515 rev. *g page 6 of 17 S34MS08G2 5. addressing notes 4. cax = column address bit. 5. pax = page address bit. 6. pla0 = plane address bit zero. 7. bax = block address bit. 8. block address concatenated with page address and plane addres s = actual page address, also known as the row address. 9. a30 for 8 gb (4 gb x 2 C ddp) (1ce). for the address bits, th e following rules apply: a0 - a11: column address in the page a12 - a17: page addr ess in the block a18: plane address (for multipl ane operations) / block address (for normal operations) a19 - a30: block address table 2. address cycle map bus cycle i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 1st / col. add. 1 a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca 5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 a8 (ca8) a9 (ca9) a10 (ca10) a11 (ca11) low low low l ow 3rd / row add. 1 a12 (pa0) a13 (pa1) a14 (pa2) a15 (pa3) a16 (pa4) a1 7 (pa5) a18 (pla0) a19 (ba0) 4th / row add. 2 a20 (ba1) a21 (ba2) a22 (ba3) a23 (ba4) a24 (ba5) a2 5 (ba6) a26 (ba7) a27 (ba8) 5th / row add. 3 (9) a28 (ba9) a29 (ba10) a30 (ba11) low low low low low document number: 002-00515 rev. *g page 7 of 17 S34MS08G2 6. read status enhanced read status enhanced is used to retrieve the status value for a previous operation in the following cases: in the case of concurrent opera tions on a multi-die stack. when two dies are stacked to fo rm a dual-die pa ckage (ddp), it is possible to run one operation on the first die, then activat e a different operation on the second die, for example: erase while read, read while program, etc. in the case of multiplane ope rations in the same die. 7. read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address in put of 00h. note if you want to execute read status command (0x70) after read i d sequence, you should input dummy command (0x00) before read status command (0x70). for the S34MS08G2 device, five read cycles sequentially output the manufacturer code (01h), and the device code and 3rd, 4th, and 5th cycle id, respectively. t he command register remains in read id mode until further commands are issued to it. figure 4. read id operation timing 8 gb table 3. read id for supported configurations density org v cc 1st 2nd 3rd 4th 5th 4 gb x8 1.8v 01h ach 90h 15h 56h 8 gb (4 gb x 2 C ddp with one ce#) x8 1.8v 01h a3h d1h 15h 5ah & |